1. Field of the Invention
This invention relates generally to the field of "turn-on circuits" used for effecting smooth time sequencing for the activation and deactivation of multiple subcircuits within an extended circuit complex. More particularly, it relates to mediating the communication between a plurality of output gates and the common conductor or bus to which said output gates are connected. More particularly yet, it relates to the field of circuits used to automatically maintain output buffer devices--which connect output gates to a common bus--in their high impedance "third state" during the periods that the common power supply voltage V.sub.cc is being powered up or powered down. The invention provides an improvement in the speed with which a power-up circuit exchanges control with the rest of the extended circuit once V.sub.cc reaches specified threshold levels. Another improvement is the greater immunity from noise-induced dips in V.sub.cc which the invention provides a power-up circuit while the extended circuit is otherwise operating properly.
2. Description of Prior Art
As background for the subsequent discussion, it is noted that the use of a tristate output buffer device ("buffer") or its equivalent is essential when connecting a TTL Transistor-Transistor Logic (TTL) output gate ("chip") to a common conductor ("bus") which is to serve as the output means for a plurality of such chips. The individual buffers and their associated circuitry are intended to ensure that only a single chip at a time is communicating with the bus and that for all practical purposes the bus cannot sense the presence of any of the other buffers and hence of their associated chips at that time. One says that only a single buffer at a time is enabled. When the buffer is enabled, it is in its active mode and can serve as a current source or a current sink to the bus, depending on what input signal it receives from its associated chip; one says that in its active mode the buffer is either "current sourcing" or "current sinking." When the buffer is in its third state, it is disabled and simply presents a high (resistive) impedance to the bus. In the properly operating multi-chip logic circuit, all of the buffers save one are disabled at any instant. Typically, a separate buffer input terminal--in addition to the buffer input terminal controlled by the buffer's associated chip--is used to switch the buffer between the active and inactive modes. This separate terminal is the Output Enable (OE) terminal; the signal to the OE terminal is supplied by the output of a separate TTL sub-circuit, the Output Enable Gate (OEG). The input to the OEG is designated "nOE." FIG. 1 shows the interconnections of the sub-circuits just described: the chip, the buffer, the OEG, and the bus. The circuit of FIG. 1 represents a single unit within a multi-chip extended circuit. Parts of the circuit not depicted in FIG. 1 are responsible for ensuring that the nOE for each OEG unit has the proper voltage value to cause the OEG to disable the buffer associated with it (unless it happens to be the sole buffer which is to be enabled). As stated above, the properly functioning extended circuit will have all but one of the buffers disabled at any one time; the remaining buffer will be enabled and--depending on its input from the chip--will constitute a current sink or a current source with respect to the bus. The OEG, like all TTL logic gates--including those present in the extended circuit under discussion here--is controlled by an input voltage which has two useful levels: a high level (binary logic one) and a low level (binary logic zero.) Similarly, the output of the OEG--and of all TTL gates--is either binary logic one (high voltage) or binary logic zero (low voltage). (Within this context, any voltage between ground and V.sub.IL is low level (binary zero) and any voltage between V.sub.IH and V.sub.cc is high level (binary one). Note that V.sub.IH is greater than V.sub.IL.) The OEG is an invertor in the sense that a binary zero input results in a binary one output and vice versa. The buffer, being a three-state device, is more complicated. For present purposes, it is only necessary to know that when the OEG output is low (binary zero) the buffer will be placed in its high impedance state--the disabled state desired during power-up and power-down.
With continuing reference to FIG. 1, note that any voltage between ground and V.sub.IL is placed on the buffer input terminal of an enabled buffer, buffer's current-sourcing circuitry will be on and its current-sinking circuitry will be off; on the other hand, if any voltage between V.sub.IH and V.sub.cc (the common power supply voltage) is placed on that buffer input terminal, that buffer's current-sourcing circuitry will be off and its current-sinking circuitry will be on. That is, when the enabled buffer has a voltage between O and V.sub.IL applied to its input terminal it will be in its current-sourcing state and when it has a voltage between V.sub.IH and V.sub.cc applied to its input terminal it will be in its current-sinking state. On the other hand, if a low-level voltage is applied to the OEG i.e., if nOE is a low level voltage, the current-sourcing circuitry and current-sinking of the associated buffer circuitry are both disabled and the buffer presents a high impedance to the bus. A high-level voltage at nOE will cause the OEG to enable the buffer, which then can respond to the signal applied to the buffer input terminal so as to appear to the bus as either a current source or as a current sink.
For the buffer input voltage range V.sub.IL to V.sub.IH the state of the enabled buffer is ambiguous: potentially, it can have both the current-sourcing and the current-sinking circuitry activated simultaneously, a situation which can load down both the bus and the common power supply. Fortunately, during normal operation, the transition between current-sourcing and current-sinking states is sufficiently rapid that this bi-phasic mode does not constitute a problem. In contrast, during power-up and to a lesser extent during power-down of the power supply the buffer input voltage can tarry in the ambiguous region for a sufficiently long period to cause loading problems and in particular to draw an excessive current spike from the common power supply. For that matter, during power-up the possibility exists that the various subcircuits, in particular the buffer subcircuits, will be energized before the OEG is capable of disabling the buffers. This means that during power-up all of the buffers may appear to the bus to be current-sourcing, current-sinking, or some combination of the two modes. Depending on the particular circuit, this may be very bad for system reliability; in most if not all TTL circuits of the type under discussion this is bad in terms of the load it places on the power supply. In general the V.sub.cc level during power-up will increases much less rapidly than the rising or falling voltages on the inputs to the various TTL circuits within the extended circuit. A slow rise-time for V.sub.cc generally results in slow rise- (or fall-) times for the voltages on nodes internal to the circuit. The combination of these two facts can cause large power supply current surges during power-up. The buffers usually have the highest amount of current sourcing and sinking capability in the type of circuit under discussion. Because of this they are likely to have the greatest power-up surges. It is for this reason that it is particularly desirable to hold the individual OEGs in the state which places the buffers in their high impedance state throughout the vulnerable part of the power-up (or power-down) transition.
Various attempts have been made to address this problem, generally by connecting yet another auxiliary sub-circuit to the array set out in FIG. 1. This is depicted schematically in FIG. 1a, where a power-up circuit is shown as an additional control for the OEG, supplementing the nOE input. The purpose of the power-up circuit/OEG combination is to hold the buffer disabled while V.sub.cc is passing through the transient-sensitive range during power-up and power-down (and "power-out"). Although the power-up circuit can be energized by a separate power supply, it is generally integrated with the other sub-circuits and energized by the same common power supply voltage V.sub.cc used by the rest of the extended multi-chip circuit. The power-up circuit must ensure that the OEG output is low during the critical values of V.sub.cc. (During normal operation the enabling/disabling signal to the OEG is produced at the OEG input nOE. During power-up and power-down, the power-up circuit in effect seizes control; it overrides the nOE.)
The conventional power-up circuit most commonly used at present is based on Houk et al. (U.S. Pat. No. 4,481,430). FIG. 2 illustrates such a circuit in isolation from the OEG to which its output V.sub.OUT is to be directed. It operates in the following manner as a function of V.sub.cc. (All transistors in this discussion are conventional bipolar junction transistors with collector, base, and emitter electrodes. Such a transistor will be described as "conducting" when current is flowing between the collector and emitter electrodes; the transistor turns on, i.e., becomes conducting, when the voltage between the base and emitter reaches a certain level, as discussed below. Since all relevant circuits will have a direct ground connection, all voltage levels identified throughout the following discussions will be implicitly referenced to ground potential.) As V.sub.cc ramps during power-up from zero toward its specified operating range, the voltage V.sub.OUT at first tracks and is equal to V.sub.cc (assuming no current is drawn at V.sub.OUT). This is because for V.sub.cc below a certain threshold level Q14 is not conducting and hence there is no current through R16.
As V.sub.cc increases with Q14 non-conducting, there comes a point at which V.sub.OUT will become sufficiently high to exert control over the OEG (to which it is directed) so as to disable the buffer. Although the value of V.sub.cc at which this power-up circuit first exerts control over the OEG can only be determined from a consideration of its connection with the OEG--as will be done below--the value of V.sub.cc at which the power-up circuit cuts out can be easily calculated in terms of the circuit elements as illustrated in FIG. 2. For reasons to be shown below, the cut-out occurs when Q14 turns on, at which point V.sub.OUT suddenly falls because of the ensuing voltage drop across R16. Q14 turns on when its base-emitter junction becomes sufficiently forward-biased that it passes current. Since the Q14 emitter is grounded, this critical condition can be stated in terms of the Q14 base voltage, V.sub.14B. The typical base-emitter voltage at which a silicon bipolar junction transistor becomes conducting at room temperature is 0.8 volts, with the exact value depending on the transistor's particular physical characteristics. Since all transistors having a particular design can be taken to have the same critical base-emitter voltage and since the transistors in the circuits to be discussed here will all be taken to be transistors of the same design, one can use the same base-emitter turn-on voltage--V.sub.BE --for all of the transistors to be discussed. (For all practical purposes, V.sub.BE is not just the base-emitter voltage at which the junction begins to conduct; it remains the base-emitter voltage regardless of the current through the forward-biased junction. V.sub.BE does vary with temperature; nominally 0.8 volts, it can be as high as one volt at low temperatures.)
Thus, Q14 begins conducting when V.sub.14B becomes equal to V.sub.BE, a condition which clamps the voltage across R15 to V.sub.BE and hence limits the current through R15 to V.sub.BE /R.sub.15. (Of course, as V.sub.cc continues to increase above its Q14 turn-on value, the current through R13 continues to increase, the augmentation being diverted as base current through Q14.) In order to calculate the value of V.sub.cc at which Q14 turns on, then, it is only necessary to determine the minimum level of V.sub.cc necessary to produce a current I.sub.15 =V.sub.BE /R.sub.15 through R15, given no other drains for current in that branch of the circuit. Note that when this occurs the voltage drop across each of the transistors Q12 and Q13 will be V.sub.BE, since--as long as current is flowing in that branch of the circuit--they will be behaving simply as two forward-biased base-emitter junctions in series. (For values of V.sub.cc less than 2 V.sub.BE these two series transistors will in effect be blocking and no current will flow through R13 and R15.) Thus, the minimum value of V.sub.cc for which Q14 will conduct, V.sub.cc(1), is given by the following equation summarizing the voltage drops along the circuit branch containing R13 and R15 when current is flowing in that branch. Generally, EQU V.sub.cc =I(R.sub.13 +R.sub.15)+2V.sub.BE ( 1a)
At the instant that the voltage drops across R.sub.15 reaches V.sub.BE, EQU V.sub.cc =V.sub.cc(1) =(V.sub.BE /R.sub.15)(R.sub.13 +R.sub.15)+2V.sub.BE( 1b) EQU I.e., EQU V.sub.cc(1) =V.sub.BE [3+(R.sub.13 /R.sub.15 ] (2)
This is based on the condition that the Q14 base current is null at V.sub.cc =V.sub.cc(1). For V.sub.cc &gt;V.sub.cc(1), the following more general relationship holds. EQU V.sub.cc =V.sub.BE [3+R.sub.13 /R.sub.15 ]+R.sub.13 I.sub.14B,(3)
where I.sub.14B is the base current through Q14, the total IR drop across R13 being (I.sub.14B +V.sub.BE /R.sub.15)R.sub.13.
Summarizing, Q14 becomes conducting when V.sub.14B reaches a level V.sub.BE. This results in V.sub.OUT falling drastically and corresponds to the point where the conventional power-up circuit yields control, the point where it "cuts out," returning OEG control to the nOE input. The behavior of V.sub.OUT as a function of V.sub.cc for the power-up circuit shown in FIG. 2 is illustrated by the graph in FIG. 2a, where V.sub.OUT is shown to follow V.sub.cc until V.sub.cc reaches the point A, at which V.sub.OUT begins to fall back toward the abscissa, leveling off at a value V.sub.SAT when V.sub.OUT reaches point B.
Referring to EQ(2), it can be seen that if R13 is chosen to have half the value of R15, then Q14 will turn on when V.sub.cc reaches a voltage of 3.5 V.sub.BE. Of course, the turn-on of Q14 and hence the cut-out of the power-up circuit will not be instantaneous and this can be a problem, especially if nOE is set at binary zero level (which can lead to the buffer being put into an ambiguous state during the "cutting out," with a resultant loading down of the power supply at that point, the very condition which was to be avoided).
FIG. 3 depicts the power-up circuit of FIG. 2 tied into a typical OEG, where the OEG is that part of the circuit to the right of the dashed vertical line. In the depiction, V.sub.OUT is connected to the base of transistor Q15 of the OEG. In turn, OE the output of the OEG therefor drives the buffer device which is coupled to the common bus of the extended multi-chip circuit. Recall that when the OEG output is low--i.e., in the binary logic zero state--the buffer is disabled. Q15 starts to conduct once its base-emitter voltage reaches V.sub.BE, that is, once V.sub.OUT reaches V.sub.BE +V.sub.SH, where V.sub.SH is the voltage drop across the forward-biased Schottky diode D16. More importantly, once V.sub.OUT reaches 2 V.sub.BE, Q19--the base of which is tied to the emitter of Q15--also starts to conduct; that is, both Q15 and Q19 are turned on. (Note also that because V.sub.OUT, that is, V.sub.15B, the base voltage of Q15, is connected to ground through the two forward-biased base-emitter junctions in series, it can never exceed 2 V.sub.BE.) When Q19 turns on, OE falls to a binary zero level and the buffer will be placed in its high-impedance state. Note further that, because the transistor Q16 is connected in exactly the same way as Q15 with respect to Q19, one can also obtain a low-level OE and hence put the buffer in its high-impedance state by setting the Q16 base voltage to 2 V.sub.BE ; this is effected by setting nOE to logic one. Restated, the buffer is disabled if either of the following two conditions is satisfied: 1) V.sub.OUT equals 2 V.sub.BE ; 2) nOE is set at logic one. When the first condition is met, one says that the power-up circuit seized control from nOE. TTL outputs typically start conducting when the common power supply voltage reaches 2 V.sub.BE. In the absence of some kind of power-up circuit it is not possible to input an nOE equal to the requisite 2 V.sub.BE until the rising V.sub.cc reaches a value slightly larger than 3 V.sub.BE. This means that in the absence of auxiliary power-up circuitry, all of the gates could be conducting as V.sub.cc passed between 2 V.sub.BE and 3 V.sub.BE on the way up to its specified operating range. Ultimately, of course, it is necessary that control over the OEG be passed back to the nOE input and hence to the extended circuit. That passing back of the control is what happens when Q14 switches on, as described above. In summary, the power-up circuit of FIG. 2 and FIG. 3 takes control of the OEG when the rising V.sub.cc reaches a level 2 V.sub.BE ; it passes control back to the nOE when the rising V.sub.cc reaches a level 3.5 V.sub.BE (given the choice of the ratio R.sub.13 /R.sub.15 set out above). The graph in FIG. 3a illustrates the key transition points. Note that it differs from the graph of FIG. 2a only in showing the clamping of V.sub.OUT at 2 V.sub.BE, and illustrating the consequential elimination of the rounded part of the FIG. 2a curve.
The power-up circuit shown in FIG. 2 and FIG. 3 is identical to the "threshold activation circuit" of Houk et al. but for the expedient of replacing diodes D1 and D2 of Houk et al. by diode-connected transistors Q12 and Q13. One advantage of the modification is that the i-v characteristics of the forward-biased base-emitter junctions of the transistors used in place of the diodes will be the same as those of the switching transistor Q14. (This fact leads to a much cleaner set of equations, since the voltage drop across all of the forward-biased junctions can now be specified as V.sub.BE.)
Note that the traditional power-up circuit acts the same way during power-down of the common power supply voltage, V.sub.cc, as it does during power-up. When the falling V.sub.cc reaches a level of 3.5 V.sub.BE, Q14 switches off (given the circuit elements selected above), V.sub.OUT jumps back to 2 V.sub.BE and the buffer is disabled. Thus, during the power-down as well as during power-up, the power-up circuit ensures that the buffer will be disabled for V.sub.cc voltages in the range 2 V.sub.BE to 3.5 V.sub.BE.
One of the factors which has to be taken into consideration in selecting the cut-out value of V.sub.cc is that it cannot be so high as to expose the circuit to being disabled every time V.sub.cc drops momentarily because of noise-induced fluctuations during normal operations. On the other hand, setting the cut-out value too low can leave the extended circuit vulnerable to power-up transients. This need to compromise is a real problem with the current power-up circuit under some circumstances. From the noise-induced fluctuations in V.sub.cc expected and from the specified operating level for V.sub.cc, one can conclude that the highest value one can select for the cut-out/cut-in voltage V.sub.cc(1) in the conventional circuit is 3.5 volts, which at low temperatures is equal to 3.5 V.sub.BE. To select it for a higher level would be to risk inadvertant cutting in of the power-up circuit during normal operation. On the other hand, the extended circuit is not always past its vulnerable region during power up by the time V.sub.cc reaches 3.5 V.sub.BE. Given those constraints, it would be desirable to have a cut-out voltage which was higher than the cut-in voltage (which would be set at 3.5 V.sub.BE).
Also a problem with the conventional power-up circuit is the relative slowness with which it cuts out, a slowness which can lead to the power supply drawing a spike of current in excess of its rated level at the time the power-up circuit is cutting out (or cutting in during power-down).
What is needed, therefore, is a power-up circuit having a high cut-out voltage, a low cut-in voltage, and a much faster switching rate than has been available previously.